Host controller

ABSTRACT

A versatile SDIO host controller capable of connecting to standardized general interfaces is provided. 
     An SDIO host controller as a one-chip semiconductor integrated circuit device comprising: at least one core of an SDIO host, the core including an SD host engine and an SD host register set and memory that control the SD host engine; a plurality of CPU interfaces that control the SDIO host; and at least one selector that selects among the CPU interfaces. In particular, the SDIO host controller preferably comprises at least an ATA interface and an ATA-SD protocol conversion engine.

This is a Divisional Application of U.S. patent application Ser. No.11/570,106 filed Dec. 6, 2007, which in turn was a 371 of PCT/JP05/17682filed Sep. 27, 2008 which claims the priority of Japanese PatentApplication 2004-281481 filed Sep. 28, 2004. The priority of allapplications is hereby claimed and all applications are herebyincorporated herein by reference.

TECHNICAL FIELD

The present invention mainly relates to an SDIO host controller device,which is a semiconductor device for controlling SD card applicationapparatus in conformity with the SD memory card or SDIO, and toapplication apparatus and so forth that use this SDIO host controllerdevice.

BACKGROUND ART

In these years, Personal Digital Assistants (PDAs) and notebookcomputers with an SD bus slot are becoming widespread. The SD bus slotconforms to the “SD memory card (Secure Digital Memory Card)” or theupward compatible “SDIO card (Secure Digital Input Output Card),” forwhich the card shape and communication protocol are defined by a uniformstandard (for convenience, slots that connect to an SD bus are hereincollectively referred to as “SD slots”). This uniform standard is hereinreferred to as the “SD standard.” More accurately, it means theinternational standard defined by the SD Association.

FIG. 9( a) is a diagram showing exemplary SD host apparatus 100 (e.g., aPDA 100 a, a notebook computer 100 b, an SD memory card reader 100 c,etc.) and SD card application apparatus 102 (a wireless LAN card 102 a,an SD memory card 102 b, a mini-SD memory card 102 c, etc.). Each SDhost apparatus 100 has an SD slot 101 with its size and shape defined bythe SD standard, and the various SD card application apparatus 102 areconnected to the SD slot.

Various peripheral apparatus have been developed as the SD cardapplication apparatus 102, for example, the wireless LAN card 102 a andthe SD memory cards 102 b and 102 c, as well as a radio broadcastreceiving card, a GPS card, and a camera card (all not shown).

Therefore, any host apparatus that have the SD slot 101 and haverequired driver software installed thereon can control these peripheralapparatus (SD card application apparatus) at any time.

For small host apparatus like mobile phones, there are standards such asthe mini-SD slot having the size slightly smaller than the normal SDslot. However, since the communication protocol itself conforms to theSD standard, whether the slot shape is of the mini-SD or the normal SDslot will not be considered unless otherwise stated.

FIG. 9( b) is a diagram schematically showing a host apparatus 100 beingconnected with an SD card application apparatus 102 via an SD bus 105.The host apparatus 100 has the SD slot 101 and is used with the SD cardapplication apparatus 102 inserted thereto.

The host apparatus 100 includes a semiconductor chip called an SDIO hostcontroller. On the other hand, the SD card application apparatus 102includes a semiconductor chip called an SD or SDIO controller (whicheveris possible but hereafter uniformly referred to as an SDIO controllerfor convenience).

The SDIO host controller and the SDIO controller are designed to performdata transfer always in a one-to-one relationship while recognizingcommands issued by each other. At this point, the SD bus differs frombuses that allow one-to-N connection, such as the USB (Universal SerialBus) described later.

Once the SDIO card application apparatus is inserted into the hostapparatus, the SDIO host controller in the host apparatus recognizes thecard application apparatus 102 by exchanging commands and data with theSDIO controller in the card.

Conventional SDIO host controllers (or SD host controllers) have beenquite simple with only minimum components, including an SDIO host core(SD host engine), one SD bus interface, one CPU interface that connectsa local bus for connecting to the CPU of the host apparatus, a clock, aregister controller, and so forth (for example, see FIG. 1 of a patentdocument 1).

-   -   [Patent Document 1]: Japanese Patent Laid-Open No.    -   [Patent Document 2]: WO03/019841

In addition to the local bus (such as a PCI bus or a generic CPU bus),the CPU of the host apparatus often has various bus interfaces thatallow high-speed bulk communication, such as an ATA interface, a USBinterface, and an IEE 1394 interface.

The USB interface is a versatile interface that can connect to storagedevices and various other apparatus, for example, input/output devicessuch as a mouse and a keyboard, printer scanners, and memory cardreader/writers.

Moreover, many of versatile operating systems that operate on the hostapparatus in these years include, as standard equipment, host controllerdevices and their device drivers for the hosts of these standardinterfaces (such as an IDE host and a USB host).

On the other hand, there are limited apparatus in which the SD businterface can be connected. Therefore, it is expected that the abilityof connecting the SD card application apparatus to those generalinterfaces will increase the variety of usage of the SD card applicationapparatus and will be applied to development of various products.

The primary technical object of the present invention is to provide aversatile SDIO host controller capable of connecting to standardizedgeneral interfaces.

DISCLOSURE OF THE INVENTION

An SDIO host controller according to the present invention is a one-chipsemiconductor integrated circuit device characterized by comprising: atleast one core 16 of an SDIO host, the core 16 including an SD hostengine 10 and an SD host register set 11 and memory 12 that control theSD host engine; a plurality of CPU interfaces 13 a, 13 b, . . . thatcontrol the SDIO host; and at least one selector (MUX) 14 that selectsamong the CPU interfaces.

The CPU interfaces preferably include at least an ATA interface and anATA-SD protocol conversion engine.

Including the ATA interface and the ATA-SD protocol conversion engine inthis manner allows a host apparatus with an IDE host to recognize theSDIO host controller according to the present invention. Then, since theSDIO host controller is recognized as an IDE device, no driver softwareor firmware need not to be installed when the target device is an SDmemory card.

In this case, the ATA interface preferably includes an Ultra DMAcontroller. This supports the Ultra DMA transfer mode and therebyincreases the data transfer rate.

Besides the ATA interface, the CPU interface preferably further includesa PCI bus interface and/or a general microcomputer interface (genericCPU interface) so that SDIO card application apparatus may be controlledvia these interfaces.

The SDIO host controller may comprise: two or more cores 16 (16 a and 16b) of an SDIO host, each core 16 including an SD host engine 10 and anSD host register set 11 and memory 12 that control the SD host engine;and two or more selectors 14. In this manner, the host apparatus mayhave two SD slots.

Thus, the SDIO host controller according to the present invention mayindependently control target devices connected to the respective SDslots by using any of the interfaces respectively.

An SD memory card duplication apparatus according to the presentinvention is an apparatus for duplicating data recorded on an SD memorycard, characterized by comprising: at least two SDIO host controllersincluding an ATA interface and an ATA-SD protocol conversion engine; alogic circuit functioning as an IDE host; and a selector circuit.

In this case, the IDE host and the selector circuit may be composed ofan FPGA (Field Programmable Gate Array). Since ATA commands required forimplementing this duplication apparatus are only ATA essential commandsand several commands attributed to the characteristics of an SD memorycard as a removable device, the duplication apparatus may be readilyimplemented with an FPGA. Of course, it may also be composed of a CPU ora microcomputer.

If a comparator and two buffers are further provided in the IDE hostcontroller of this apparatus so that address-by-address data is comparedbetween a duplication source and a duplication target on a hardwarebasis, verification may be faster than verification on a software basis.

A method of duplicating a memory card according to the present inventionis, in a memory card duplication apparatus comprising: an IDE hostcontroller; a reading memory card host controller connected with the IDEhost controller via an ATA interface; a writing memory card hostcontroller connected with the IDE host controller via an ATA interfaceand directly connected with the reading host controller by a data bus;and a selector circuit, characterized by comprising the steps of:

-   -   (a) the IDE host controller issuing a read DMA command to the        reading host controller that reads a memory card containing data        to be duplicated;    -   (b) on receiving the read DMA command (Read DMA), the reading        host controller reading the data to be duplicated from the        memory card containing the data and accumulating the data in a        buffer of the reading host controller;    -   (c) once the data is accumulated, the reading host controller        making a DMA request signal (dmarq1);    -   (d) after receiving the DMA request signal (dmarq1), the IDE        host controller issuing a write DMA command (write DMA) to the        writing host controller; and    -   (e) after receiving a DMA request signal (dmarq2) from the        reading host controller, the IDE host controller issuing a data        transfer start signal (dmack) while electrically coupling        “iordy1” and “dior2” by switching the selector circuit.

Thus, what is characteristic is that, while the IDE host controllerpasses the commands, data during the data transfer is directlytransferred from the reading host controller to the writing hostcontroller without the intervention of the IDE host controller. In thismanner, since data is transferred on a hardware basis, data transferefficiency is extremely high, and fast transfer is possible.

An SD memory card reader/writer according to the present invention ischaracterized in that an SDIO host controller according to the presentinvention (comprising an ATA interface and an ATA-SD protocol conversionengine) and a USB controller having an ATA bridge function are connectedby an Ultra DMA bus via respective ATA interfaces of the controllers.

Since the USB controller is being recognized by a USB host apparatus, nodriver software or firmware is required. In addition, the Ultra DMAtransfer mode dramatically increases the reading and writing speed.

It is expected that the SDIO host controller device according to thepresent invention will further enhance the versatility compared with theconventional art and will be applied to various host apparatus.Furthermore, novel application products that use the SDIO hostcontroller device according to the present invention may be provided,for example, an SD memory card duplication apparatus capable ofhigh-speed duplication of SD memory cards.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a diagram showing an example of functional blocks of an SDIOhost controller according to the present invention;

FIGS. 2( a) to (d) are diagrams showing practical implementations thatuse the host controller illustrated in FIG. 1;

FIG. 3( a) is a diagram showing an exemplary SD memory card duplicationcircuit that uses the SDIO host controller device according to thepresent invention, and FIG. 3( b) is a diagram showing an exemplaryhardware implementation for providing the circuit configuration of FIG.3( a);

FIG. 4( a) is a diagram showing a protocol timing chart for ATA signalsissued by an FPGA, and FIG. 4( b) is a diagram for describing the stateof a circuit during data transfer;

FIG. 5 shows a circuit configuration in which FIG. 3( a) is expanded toallow duplication on a plurality of memory cards;

FIG. 6 is a diagram showing an exemplary hardware implementation of adata comparator (verifier);

FIG. 7( a) is a block diagram showing an example of an SD memory cardreader/writer that uses the SDIO host controller according to thepresent invention, and FIG. 7( b) is a variation of FIG. 7( a) in whichcommunication with a USB controller is performed via a generalmicrocomputer interface rather than an ATA interface;

FIG. 8( a) shows the SD memory card reader/writer 70 provided with anIDE connector 76 of e.g., 2.5 inch and connected to a hard disk recorder80 by an ATA/IDE bus, and

FIG. 8( b) shows the SD memory card reader/writer further provided witha slot 77 for a PCI bus interface; and

FIG. 9( a) is a diagram showing exemplary SD host apparatus 100 and SDcard application apparatus 10, and FIG. 9( b) is a diagram schematicallyshowing a host apparatus 100 being connected with an SD card applicationapparatus 102 via an SD bus 105.

DESCRIPTION OF SYMBOLS

-   10 SD host engine-   11 SD host register (set)-   12 memory (buffer)-   13 CPU interface-   13 a ATA interface (ATA/SD engine)-   13 b PCI interface-   13 c general microcomputer interface (generic PCI interface)-   18 SDIO host controller-   20 (20 a, 20 b) SD slot-   21 IDE connector-   22 PCI slot terminal-   31 (31 a, 31 b, 31 c) host controller-   32 (32 a, 32 b) SD memory card-   33 FPGA (or CPU)-   34 selector circuit-   35 IDE host-   36 arbitration circuit (arbitration controller)-   37 comparator-   38 (38 a, 38 b) buffer-   70 SD memory card reader/writer-   71 SDIO host controller-   73 USB controller-   74 regulator IC-   100 SD/SDIO host apparatus-   100 a PDA-   100 b notebook computer-   100 c SD memory card reader/writer-   101 SD slot-   102 SD/SDIO card application apparatus-   102 a SD memory card-   102 b SDIO card-   103 SD/SDIO host controller-   104 SD/SDIO controller-   105 SD bus

BEST MODE FOR CARRYING OUT THE INVENTION First Embodiment

First, description will be given of an overview of an exemplary SDIOhost controller device (which may be simply referred to as a “hostcontroller” hereafter) according to the present invention, and itstypical implementations.

[Exemplary SD Host Controller]

FIG. 1 shows an example of the SDIO host controller according to thepresent invention. As shown in this figure, the controller 18 is aone-chip semiconductor device which has functional blocks including twoSD host cores 16. Each core includes an SD protocol engine (an SD hostengine 10) of an SD host, and an SD host register set 11 and memory(such as SRAM) 12 that control the SD host engine (like functionalblocks are denoted with like reference numerals and distinguished bysubscripts a and b). The functional blocks also include three CPUinterfaces (an ATA interface 13 a, a PCI interface 13 b, and a generalmicrocomputer interface 13 c) that control the SD host, and selectors(MUXs 14 a and 14 b) that selects among the CPU interfaces. A prototyperesulted in a 144-pin CSP (Chip Size Package) with dimensions of 8 mm by8 mm by 1.0 mm.

Minimum required parts for a host apparatus with an SD slot to controlan SD card application apparatus are: one SDIO host core enclosed with adashed line; an interface for connecting to a local bus, such as a PCIinterface; and a peripheral circuit such as a clock reset circuit. Someone-chip devices having these parts thereon are already commerciallyavailable.

However, this host controller 18 is characterized by having a pluralityof CPU interfaces that control the SD host, i.e., having the “ATAinterface,” in addition to the “PCI bus interface” and the “generalmicrocomputer interface” included in the specifications of the SDstandard.

Description of Functional Blocks

Each functional block will be described below.

(a) SD Host Engine

This is a part that issues SD commands to a target application apparatus(an SD card application device) to control the target applicationapparatus, and it is the heart of the SDIO host controller.

(b) SD Host Register Set

This is a register specification that conforms to the SD standard (SDHost ver.1.0). Device drivers provided as standard equipment in ageneral operating system may be directly used.

(c) Memory (Buffer)

This is composed of SRAM and includes two banks of double buffer memory(512 bytes). The memory may be internal or external to the SD host core:whichever is possible. As long as the memory functions as a buffer, thecomposition is not limited to SRAM.

(d) Clock Reset Section

To adapt to the version upgrade of the SD standard (PhysicalSpecification ver.1.01), the clock frequency has been increased to 50MHz from the previous 25 MHz and allows faster data transfer. Withoutthe limitation of the standard, it could be operated at still higherspeed.

(e) PCI Bus Interface

The PCI bus (Peripheral Component Interconnect bus) is a specificationof an internal bus used in data transfer between the CPU system andperipheral apparatus. The PCI bus interface of the SDIO host controlleraccording to the present invention supports the DMA (Direct MemoryAccess) transfer mode.

(f) General Microcomputer Interface

The general microcomputer interface (generic CPU interface) is aninterface for connecting to a microcomputer. The microcomputer istypically embedded in the host apparatus (embedded type). Themicrocomputer can know the content of the SD host registers (referencenumeral 11 in FIG. 1) through the general microcomputer interface. Thegeneral microcomputer interface of the SDIO host controller according tothe present invention supports the DMA (Direct Memory Access) transfermode.

The above (a) to (f) are the basic composition of the functional blocksof the SDIO host controller that conforms to the SD standard.

(g) ATA Interface

The ATA interface (which may be simply referred to as an “ATA”hereafter) is one of CPU internal bus interfaces and is typically aninterface for connecting a storage device such as a hard disk drive. TheATA is used by connecting an IDE device (such as a hard disk drive) to astandardized connecter called IDE. The host controller for the ATA isherein referred to as an“IDE host.”

The ATA interface of the SDIO host controller according to the presentinvention supports the PIO transfer mode (Programmed I/O). In addition,it includes a dedicated DMA controller, thereby supporting the Ultra DMAtransfer mode. It may also be configured to support thesingle-/multi-word DMA transfer mode.

(h) ATA-SD Protocol Conversion Engine

Even though the ATA interface is provided, the SD host engine must beable to interpret ATA commands in order for commands and data to betransmitted to the SD bus. Therefore, a protocol conversion engine forconverting ATA commands into SD commands is needed.

The ATA-SD protocol conversion engine is configured such that the SDhost engine issues a predetermined SD command in response to a commandreceived at the ATA interface. For example, protocol conversion isperformed by predefining a rule (command table) for the SD protocolengine to “issue ‘command 18 (CMD 18)’ and ‘command12 (CMD 12)’ if thecommand “READ SECTOR” is received.

Table 1 shows exemplary ATA commands supported by the ATA-SD protocolconversion engine. As commands required by the IDE host, it supports ATAdevice essential commands, as well as commands for notifying of thestatus of the power management feature set and the status of the SDmemory card (connected or disconnected, since the card is removable)(e.g., commands for notifying that the SD memory card is disconnected,the SD memory card has been changed, the SD memory card iswrite-protected, etc.).

TABLE 1 Protocol ATA Code CHECK POWER MODE ND M, P C0h EXECUTE DEVICEDIAGNOSTIC ND M 90h FLUSH CACHE ND M E7h IDENTIFY PACKET PI M ECh IDLEND M, P E3h IDLE IMMEDIATE ND M, P E1h INITIALIZE DEVICE PARAMETER ND M91h GET MEDIA STATUS ND R EDh MEDIA EJECT ND R DEh READ DMA DM M C8hREAD MULTIPLE PI M C4h READ SECTOR(S) PI M 20h READ VERIFY SECTOR(S) NDM 40h SEEK ND M 70h SET FEATURES ND M EFh SET MULTIPLE MODE ND M C6hSLEEP ND M, P E6h STANDBY ND M, P E2h STANDBY IMMEDIATE ND M, P E0hWRITE DMA DM M CAh WRITE MULTIPLE PO M C5h WRITE SECTOR(S) PO M 30h NDNon-data Command Protocol M: Must PI: PIO data-in Command Protocol P:Power Management feature set PO: PIO data-out Command Protocol R:Removable Media Status Notification feature set DM: DMA Command Protocol

Tables 2 and 3 are exemplary ATA-SD command conversion tables.

TABLE 2 Command Table (ND) SD ATA Command SDIO Host Controller CommandCHECK POWER MODE Report present mode. N/A IDLE Return to idle state N/A(resume clock). Set a timer. IDLE IMMEDIATE Return to idle state N/A(resume clock). SLEEP Control clock N/A (minimum power consumption).STANDBY Same as SLEEP since N/A STANDBY mode is not implemented. STANDBYIMMEDIATE Same as SLEEP since N/A STANDBY mode is not implemented.EXECUTE DEVICE Issue to both cards and CMD13 DIAGNOSTIC check theirstate. (SEND_(—) STATUS)? SET Sub code; 03h Set transfer mode N/AFEATURES Sub code; 31h Disable Media Status N/A Notification Sub code;95h Enable Media Status N/A Notification FLUSH CACHE Return Status afterN/A FIFO data is written. READ VERIFY SECTOR(S) Confirm accessibilityCMD18 + of LBA and return CMD12 Status. GET MEDIA STATUS Return Statusfrom N/A signals such as WP and CD. MEDIA EJECT Nothing specific. N/AINITIALIZE DEVICE Not required if CHS N/A PARAMETERS conversion. SEEKN/A N/A

TABLE 3 Command Table (PI/PO/DM) Data transfer must be done by CMD18/25because it is much faster than CMD17/24 and make HW simple. ATA SDCommand SDIO Host Controller Command IDENTIFY Transfer CSD info when theN/A DEVICE initialization process READ Set transfer block counter byCMD18 + SECTOR(S) sector count and start transfer CMD12 by CMD18.Decrement counter for each block and stop transfer by CMD12 when counterreach up. WRITE Same as above. CMD25 + SECTOR(S) CMD 12 SET Setinterrupt trigger counter N/A MULTIPLE by this command. MODE READ Sameas READ SECTOR(S) command CMD18 + MULTIPLE except interrupt is generatedCMD 12 by a count defined by SET MULTIPLE MODE. WRITE Same as above.CMD25 + MULTIPLE CMD12 READ Same as READ SECTOR(S) command CMD18 + DMAusing DMA or Ultra DMA mode which CMD12 is set by SET FEATURE command.WRITE Same as above. CMD25 + DMA CMD12

Addressing methods generally include CHA (Cylinder Header Addressing)and LBA (Logical Block Addressing). The SD memory cards employ LBA, andthe IDE host apparatus employs CHS. Therefore, address conversion fromCHA to LBA is necessary. It should be noted that the conversion must beperformed such that the capacity of the SD memory is not exceeded whenthe IDE host apparatus accesses the last address in CHA.

In addition, if the command response from the SDIO card applicationapparatus is late, measures should be taken such as terminating theprocessing after certain time period to prevent the system of the hostapparatus from hang-up.

MUX:

As described above, the SDIO host controller according to the presentinvention has a plurality of interfaces. Therefore, which interface isapplied to communication should be set with a selector switch (e.g. , aDIP switch) in advance. The MUX acts as a selector for selecting amongthe interfaces, so to speak.

ATA Transfer Modes

Now, a brief description of the ATA transfer modes will be provided. TheATA transfer modes include (i) the PIO transfer mode in which the CPUdirectly performs data transfer, and (ii) the Ultra DMA transfer modeimplemented by a dedicated DMA controller. Control methods and timingfor the ATA signals are defined in detail for each transfer mode.

(i) PIO Transfer Mode

The PIO (Programmed I/O) transfer mode involves the CPU directlyperforming data transfer. IN/OUT instructions of the CPU are used toread from and write to a buffer memory space, and the reading andwriting are repeated by LOOP instructions or the like. Since this methodcauses access cycles for the registers and the main memory to begenerated on the system bus, the speed of the system bus governs thetransfer rate.

(ii) Ultra DMA Transfer Mode

The ATA includes an interface for high-speed data transfer called theUltra DMA transfer, and a data transfer mode using the Ultra DMAinterface is called the Ultra DMA transfer mode. In this mode, a DMAcontroller inside an IDE controller that acts as the bus master on thePCI bus performs data transfer. The data transfer on the PCI bus equalsthe data transfer performed by the normal PCI bus master. Since accesseson the side of the ATA device are performed by the IDE controller itselfwith its own DMA controller irrespective of the system bus, the accesscycles generated on the system bus are only those for the main memory.This allows faster data transfer than in the cases of other transfermodes.

There is also the single-/multi-word DMA transfer mode, which will notbe described here (although named as DMA, it is completely differentfrom the Ultra DMA transfer mode).

Referring to FIGS. 2( a) to (d), description will be given below ofpractical implementations that use the host controller illustrated inFIG. 1.

First Implementation

While there are various host apparatus, host apparatus having aninternal hard disk drive usually include an IDE host and therefore anATA interface, as described above.

As shown in FIG. 2( a), the above-described host controller 18 shown inFIG. 1 may be applied to those apparatus with an IDE host. Then,connection can be made from an ATA interface 21 to an IDE host 25 of ahost apparatus 19 a via an ATA Ultra DMA bus (ATA U-DMA bus).

The IDE host 25 is being recognized by the CPU or the like (not shown)of the host apparatus 19 a from the beginning, and the protocolconversion between the ATA and the SD is performed by the hostcontroller 18. Therefore, no driver software or firmware for recognizingthe SD host needs to be installed on the host apparatus.

Since the ATA is basically an interface for connecting a storage device,its typical implementation is connection to SD memory cards as in FIG.2( a) rather than to SDIOs. However, connection to SDIOs is alsopossible if they have a memory function.

Thus, according to the usage as in this implementation, the SD memorycards can replace a conventionally connected hard disk to reduce thesize of the apparatus. Alternatively, the advantage of easy removabilityof the SD memory cards can be taken to use the SD memory cards as anauxiliary storage medium for the hard disk.

In addition, since the Ultra DMA transfer with a high transfer rate isused, the speed of data write/read is increased compared to datawrite/read on the SD memory cards via a conventional local bus on asoftware basis. This speedup is perceptively dramatic.

Second Implementation

If a host apparatus includes an IDE host and a microcomputer (the hostof a generic CPU) or PCI host, interfaces for these two may be used toconnect to the host controller.

As shown in FIG. 2( b), the above-described host controller 18 shown inFIG. 1 may be applied to a host apparatus 19 b having both an IDE hostand a CPU or microcomputer with a PCI bus. Then, connection can be madefrom an ATA interface 21 to the IDE host 25 of the host apparatus 19 bvia an ATA Ultra DMA bus (ATA U-DMA bus), and connection can be made tothe CPU or the like of the host apparatus 19 b via a PCI bus 22 (or ageneric CPU bus (not shown)).

Most personal computers in recent years include, as standard equipment,both the IDE host 25 and the CPU with the PCI bus. Even a host apparatuswithout a PCI bus may connect to the general microcomputer interface ofthe host controller from a general port such as a GPIO if the hostapparatus has a microcomputer.

Thus, connecting the host controller by using the two interfaces in thismanner allows operating an SD memory card via the ATA interface, as wellas controlling various SDIO card application apparatus (e.g., a wirelessLAN card) via the PCI or general microcomputer interface.

Third and Fourth Implementations

As shown in FIG. 2( c), connection can also be made to two SDIO cardapplication apparatus via a PCI bus interface. In this manner, a singlehost apparatus can have two SD bus slots that are SDIO-capable. Thisimplementation is used mainly when the SDIO host is connected to ageneral-purpose personal computer.

As shown in FIG. 2( d), connection can also be made to two SDIO cardapplication apparatus via a general microcomputer interface such as aGPIO port of a microcomputer. In this manner, two SDIO hosts can beincluded in a single host apparatus. This implementation is used mainlywhen the SDIO host is embedded in an apparatus without a PCI bus, suchas a PDA or a digital video camera.

The above implementations are only exemplary, and none of them areexclusive. Appropriate combinations, modifications, and alterations ofthese implementations in the light of the normal creative level of thoseskilled in the art will also fall within the scope of the presentinvention.

EXAMPLES

Description will be given below of implementations of applicationproducts that use the SDIO host controller device according to thepresent invention.

Second Embodiment Memory Card Duplication Apparatus

As described above, the SDIO host controller illustrated in the firstembodiment can directly control SD card application apparatus by usingthe ATA commands. Therefore, two SDIO host controller devices and oneATA host (a logic circuit for transmitting the ATA commands) may becombined to create a dedicated circuit for duplicating an SD memory card(a duplication apparatus).

Typically, when data in an SD memory card is duplicated on (copied into)another SD memory card, the entire data is first read into the hostapparatus. Then, the other SD memory card into which the data is copiedis inserted into the host apparatus, and the entire data is written tothe other SD memory card. The data duplication is thus completed.However, this approach involving reading and writing of data on asoftware basis takes time and effort.

Coupling the host controllers by the ATA interface to create a dedicatedcircuit for transferring data in the Ultra DMA transfer mode canincrease the speed and reduce the effort.

Example 1 SD Memory Card Duplication Method (1:1) [CircuitConfiguration]

FIG. 3( a) shows an exemplary SD memory card duplication circuit thatuses the SDIO host controller devices according to the presentinvention. This circuit is a dedicated circuit by which data recorded ona memory card is duplicated on (copied into) another memory card. Thiscircuit includes two SDIO host controllers 31 a and 31 b, a logiccircuit, e.g., an FPGA 33, and one selector circuit 34.

As shown in this figure, the FPGA 33 and the two host controllers 31 aand 31 b are coupled by a bus for data transfer (a data bus), as well assignal lines for transmitting and receiving the ATA commands.

All the signal lines conform to the ATA standard. For the sake ofsimplicity, signal lines for transmitting a chip select signal (CS[1:0])used to access the registers of the ATA or an address signal (DA[2:0])used to access data or a data port are not shown.

Furthermore, the two host controllers 31 a and 31 b are connected witheach other such that their respective ATA interfaces (specifically, theUltra DMA interfaces) are physically direct-coupled. Data is thustransferred in the Ultra DMA transfer mode.

The first SDIO host controller 31 a is for reading, and the first SDmemory card 32 a, which is the duplication source (the master), isconnected thereto. The second SDIO host controller device 31 b is forwriting, and the second SD memory card 32 b, which is the duplicationtarget (the copy target) is connected thereto.

FIG. 3( b) shows an exemplary hardware implementation for providing theabove circuit configuration. As in this figure, the simplestimplementation is to embed an IDE host 35 that supports several simpleATA commands into the FPGA 33. Of course, the selector 34 may beembedded into the FPGA 33. When the bus is shared, it is necessary toprovide an arbitration circuit (an arbitration controller) 36 along withthe IDE host 35.

[Data Transfer Method]

The FPGA 32 uses the ATA command signals to control the timing ofstarting and terminating data transfer between the two SDIO hostcontroller devices 31 a and 31 b. However, data transferred duringduplication is directly transferred via the respective Ultra DMAinterfaces of the two SDIO host controller devices (i.e., the dataitself bypasses the FPGA 32).

This circuit uses the ATA interface of the host controller to controlinput/output of data to/from the SD memory cards with the ATA commandsissued by the central control chip (the IDE host in FIG. 3). With theATA commands, the duplication source is set to the “Read mode” of theUltra DMA, and the copy target is set to the “Write mode” of the UltraDMA. By the time the transfer is ready, dmarq signals are issued.Respective dmack signals are controlled to manage the start and end ofthe data transfer.

Each of the dmack and dmarq signals is one of ATA signal names. They arein a handshake relationship, i.e., the data transfer is started whenboth signals are made.

Specifically, a strobe signal is realized using data signal lines: iordyfor the transmitting side and dior for the receiving side. The datatransfer protocol is generally implemented in the following procedure.

FIG. 4( a) is a diagram showing a protocol timing chart for the ATAsignals issued by the FPGA.

(a) The FPGA 33 issues a read DMA command to the reading host controllerdevice 31 a.

(b) On receiving the read DMA command (Read DMA), the reading hostcontroller 31 a reads data from the memory card 32 a, which is the copysource, and accumulates the data in the buffer 12 a of the hostcontroller 31 a.

(c) Once the data is accumulated in the buffer, the host controller 31 amakes a DMA request signal (dmarq1) This allows the FPGA 33 to know thedata transfer is ready and to make a DMA request signal (dmarq1).

(d) After receiving the DMA request signal (dmarq1), the FPGA issues awrite DMA command (Write DMA) to the writing host controller 31 b.

(e) After receiving a DMA request signal (dmarq2) from the reading hostcontroller device, the FPGA issues a data transfer start signal (dmack)while electrically coupling “iordy1” and “dior2” by switching theselector circuit.

FIG. 4( b) is a diagram for describing the state of the circuit duringthe data transfer, in which the selector circuit is shown electricallycoupling “iordy1” and “dior2.” Here, “iordy1” operates as a data strobesignal.

In this manner, the selector 34 is switched just before the start of thedata transfer, so that the path is switched to transmit the strobesignal to the writing host controller 31 b rather than to the FPGA (thisreleases the FPGA from the data bus during the data transfer).

In brief, the FPGA 33 communicates with the host controllers 31 a and 31b with ATA commands until the data transfer is ready. Just before thedata transfer, the selector circuit 34 is switched to directly couplethe Ultra DMA interfaces of the host controllers 31 a and 31 b. Thisallows the Ultra DMA transfer without the intervention of the FPGA 33.According to this data transfer mode, the strobe signal and data signalare directly transferred from the first SDIO host controller device 31a, i.e., the copy source, to the second SDIO host controller device 31b, i.e., the copy target. Since the transferred data bypasses the FPGA,the data transfer rate as well as the transfer efficiency are high.

When the apparatus configuration of this example 1 is employed, even ifthe SDIO host controller devices include two SDIO host cores, the masterSDIO host controller device 31 a uses only one core and does not use theother one.

Example 2 SD Memory Card Duplication Apparatus (1:N)

The example 1 has been described for the case where the duplicationsource card and the duplication target card is in a one-to-onerelationship. This can be expanded to duplication from one duplicationsource card to a plurality of cards at the same time.

FIG. 5 shows a circuit configuration in which FIG. 3( a) is expanded toallow duplication on a plurality of memory cards. Second and third SDIOhost controllers 51 b and 51 c for writing (duplication targets) areshown to be connected to the first SDIO host controller 51 a for reading(duplication source). Of course, this circuit may be implemented with asingle FPGA as in FIG. 3( b).

By connecting more DMA interfaces along with branching the selectorcircuits and dior and diow signals, further more cards may be duplicatedat the same time.

Variations of Examples 1 and 2

The SDIO host controller illustrated in the first embodiment includestwo SD host cores. On the other hand, the ATA specifications include twoIDE connectors called primary and secondary. Therefore, seen from theATA host, application apparatus connected to the two SD host coresrespectively may be used with distinction of the master/slave.

However, when a dedicated apparatus of the SD memory card duplicationcircuit as in the example 1 or2 is configured, settings may be modifiedto write the same data to both cards by the writing host controllerwithout distinction of the master/slave. In this manner, a singlewriting host device may be used to write the same data to two cards. Forthe reading host controller, the master/slave needs to be distinguishedand a situation of using the both at the same time is not likely.

Example 3 Verification

In verifying the written data to check for the correctness of thecopying, there has been a problem that the verification is lengthybecause it is done on a software basis.

As shown in FIG. 6, a comparator 37 and buffers 38 a and 38 b may beprovided in the IDE host composed of the FPGA. These allowaddress-by-address comparison of the data between the duplication sourceand target on a hardware basis, thereby allowing faster verification.

If an address having a data mismatch is discovered as a result of theverification, an error flag is set and an error signal is transmitted.This signal may be used to light an LED, to display the mismatch addresson a liquid crystal display, and so forth.

Since all the cases described in the examples 1 to 3 illustrate theinvention made in the course of developing the SDIO host controller, thedescription has assumed the use of SD memory cards. However, the sameoperational procedure may be followed to configure these memory cardduplication apparatus even in the case where the first and second hostcontroller device with an ATA interface (and a command interpreter)includes a host interface other than the SDIO, for example, a CompactFlash® or a Memory Stick®.

Third Embodiment SD Memory Card Reader/Writer

The USB (Universal Serial Bus) interface is a versatile interfaceexternal to the CPU that can connect to various apparatus. There havebeen SD memory card reader/writers that connect to a USB terminal.However, they include a USB controller and an SD host controller, andinvolve converting data received by the USB into SD data such as byfirmware and transmitting the data to the SD such as via a generalmicrocomputer interface. Thus, since the data is converted on a softwarebasis, reading and writing is slow and is on the order of 8Mbyte/sec atthe most.

On the other hand, various USB controllers have been developed,including what is called a bridge chip that allows bridge conversionbetween the ATA host and the USB.

The SDIO host controller according to the present invention includes theATA interface and the ATA-SD protocol conversion engine. Therefore, aUSB controller with the ATA bridge function and the SDIO host controlleraccording to the present invention may be connected via the ATA-UltraDMA bus.

FIG. 7( a) is a block diagram showing an example of an SD memory cardreader/writer that uses the SDIO host controller according to thepresent invention. As shown in this figure, the card reader/writer 70includes a host controller 71 according to the present invention (whichmay be the same as the one denoted by reference numeral 18 in FIG. 1), aUSB controller (ATA-USB 2.0) 73 with the ATA bridge function, and SDslots 75 a and 75 b. The host controller (SD memory card-capable) andthe USE controller are connected with each other by an Ultra DMA bus viathe ATA interface.

Since the power can be supplied from the USB terminal, a regulator IC 74is adapted to provide the power to the entire apparatus. SD memory cards102 a are connected to the host controller on the SD side.

The USB host resides in the host apparatus (e.g., a PC) and communicatesaccording to the BOT (Bulk Only Transfer) protocol. The USB varies inits class specifications depending on the type of the apparatus to beconnected. The BOT protocol is a data transfer protocol class (massstorage class) for data transfer to/from a mass storage device.

In this manner, since the data transfer is performed on a hardware basiswith connection via the ATA-Ultra DMA bus, the transfer rate isdramatically increased compared to conventional SD memory cardreader/writers.

Variation

FIG. 7( b) is a variation of FIG. 7( a) in which the communication withthe USB controller is performed via a general microcomputer interfacerather than the ATA interface.

In this manner, the microcomputer included in the USB controller candirectly control the SDIO registers of the host controller. Therefore,not only SD memory cards but also SDIO card application apparatus (e.g.,an SDIO wireless LAN card) can be operated.

It is noted that some SDIO card application apparatus connected mayrequire developing firmware, or developing driver software for the hostapparatus. It may also be necessary to select among the communicationprotocols for use in communication with the USB controller, for example,to employ the BOT protocol or to employ another communication protocol.

Further Example

Like USB controllers with the IDE host, there are also IEEE 1394controllers with the IDE host. Therefore, according to the aboveexamples and their variations, replacing the USB controller with an IEEE1394 controller realizes an IEEE 1394-capable ultrafast SD cardreader/writer.

Fourth Embodiment

Since the SD memory card reader/writer described in the third embodimentincludes the ATA interface, it is quite easy to provide an IDE connectorfor connecting with the ATA interface of the host controller.

FIG. 8( a) shows the SD memory card reader/writer 70 described in FIG.7( a) provided with an IDE connector 76 of e.g., 2.5 inch and connectedto a hard disk recorder 80 by an ATA/IDE bus. The hard disk recorder 80includes a hard disk drive 81 and a CPU 82 (the IDE host), which areconnected via an ATA interface.

According to the ATA specifications, one IDE connector may have up totwo devices (device 0 and device 1) connected thereto. The device 0 iscalled primary and the device 1 is called secondary.

Therefore, when the SD memory card reader/writer shown in FIG. 8( a) isconnected as a secondary device for the hard disk recorder 80, the harddisk recorder 80 can immediately recognize the host controller 81 andcontrol the SD memory cards.

Of course, the connected apparatus is not limited to a hard diskrecorder but may be any host apparatus with an IDE host. Examples mayinclude apparatus that basically have a hard disk drive connectedthereto, such as a personal computer, an audio player with an internalhard disk, and so forth.

It is noted that the usage as shown in FIG. 8( a) is a typical exampleof the first implementation (FIG. 2( a)) in the above-described firstembodiment.

As in FIG. 8( b), further providing a slot 77 for a PCI bus interfacefacilitates connection to various host apparatus via various CPUinterfaces, thereby further facilitating the development of hostapparatus.

INDUSTRIAL APPLICABILITY

Since the SDIO host controller device according to the present inventionhas a plurality of CPU interfaces including an ATA interface, it can bereadily connected to various host apparatus. In addition, since theATA-SD protocol conversion engine is provided, the SDIO host controlleraccording to the present invention is only recognized as an IDE deviceby the IDE host and therefore does not require driver software orfirmware.

Furthermore, when a connection is made to a bus external to the hostapparatus via a USB-ATA bridge chip, the data transfer rate isdramatically increased from the conventional data transfer rate, becausethe ATA-SD protocol conversion engine performs protocol conversion on ahardware basis.

Thus, the SDIO host controller device according to the present inventioneliminates the need of developing driver software or firmware andfacilitates the developing environment for SD host apparatus to agreater extent. The industrial applicability is significant.

FIG. 1

-   10 a SD HOST ENGINE-   10 b SD HOST ENGINE-   11 a SD HOST REGISTER SET-   11 b SD HOST REGISTER SET-   12 a MEMORY (BUFFER)-   12 b MEMORY (BUFFER)-   13 a ATA I/F (U-DMA)    -   ATA-SD ENGINE-   13 b PCI I/F (with DMA)-   13 c GENERAL MICROCOMPUTER I/F (with DMA)-   14 a MUX (SELECTOR)-   14 b MUX (SELECTOR)-   15 CLOCK RESET-   #1 TO SD SLOT-   #2 TO SD SLOT

FIG. 2

-   19 a (HOST APPARATUS)-   19 b (HOST APPARATUS)-   19 c (HOST APPARATUS)-   19 d (HOST APPARATUS)    FIG. 3( a)-   31 a (HOST CONTROLLER)-   32 a (MEMORY CARD)-   34 (SELECTOR CIRCUIT)-   #1 COPY SOURCE-   #2 COPY TARGET-   #3 SOURCE-   #4 SINK    FIG. 3( b)-   34 (SELECTOR CIRCUIT)-   35 IDE HOST-   36 ARBITRATION CIRCUIT    FIG. 4( a)-   31 a (FOR READING)-   31 b (FOR WRITING)-   #1 SIGNAL NAME-   #2 (a)-   #3 (c)-   #4 (d)-   #5 TRANSFERRING (DIRECT TRANSFER)-   #6 (e) DATA TRANSFER START SIGNAL-   #7 FPGA RELEASES DATA BUS DURING TRANSFER    FIG. 4( b)-   31 a (HOST CONTROLLER)-   32 a (MEMORY CARD)-   34 (SELECTOR CIRCUIT)-   #1 COPY SOURCE-   #2 COPY TARGET-   #3 SOURCE-   #4 SINK

FIG. 5

-   31 a (HOST CONTROLLER)-   34 (SELECTOR CIRCUIT)-   #1 COPY SOURCE-   #2 COPY TARGET 1-   #3 COPY TARGET 2-   #4 SOURCE-   #5 SINK 1-   #6 SINK 2

FIG. 6

-   34 SELECTOR CIRCUIT-   35 (IDE HOST)-   36 (ARBITRATION CIRCUIT)-   37 (COMPARATOR)-   38 a (BUFFER)-   #1 ERROR SIGNAL    FIG. 7( a)-   #1 TO PC    FIG. 7( b)-   #1 TO PC    FIG. 8( a)-   80 (HARD DISK RECORDER)    FIG. 8( b)-   77 (PCI SLOT)-   #1 TO PC    FIG. 9( a)-   100 (SD/SDIO HOST APPARATUS)-   102 (SD/SDIO CARD APPLICATION DEVICES)-   102 a WIRELESS LAN-   102 b SD MEMORY-   102 c MINI-SD MEMORY    FIG. 9( b)-   103 (SD/SDIO HOST CONTROLLER)-   104 (SD/SDIO CONTROLLER)-   105 (SD BUS)

1. A method of duplicating a memory card in a memory card duplicationapparatus comprising: an IDE host controller; a reading memory card hostcontroller connected with the IDE host controller via an ATA interface;a writing memory card host controller connected with the IDE hostcontroller via an ATA interface and directly connected with the readinghost controller by a data bus; and a selector circuit, the methodcharacterized by comprising the steps of: (a) the IDE host controllerissuing a read DMA command to the reading host controller that reads amemory card containing data to be duplicated; (b) on receiving the readDMA command (Read DMA), the reading host controller reading the data tobe duplicated from the memory card containing the data and accumulatingthe data in a buffer of the reading host controller; (c) once the datais accumulated, the reading host controller making a DMA request signal(dmarq1); (d) after receiving the DMA request signal (dmarq1), the IDEhost controller issuing a write DMA command (Write DMA) to the writinghost controller; and (e) after receiving a DMA request signal (dmarq2)from the reading host controller, the IDE host controller issuing a datatransfer start signal (dmack) while electrically coupling “iordy1” and“dior2” by switching the selector circuit.